The present invention relates to a BiCMOS, i.e., bipolar and complementary metal oxide semiconductor (CMOS), device, and in particular to a BiCMOS device in which the capacitor component thereof comprises a stacked polysilicon-polysilicon (Poly-Poly)/metal oxide semiconductor (MOS) capacitor. The present invention also provides a method of fabricating a stacked Poly-Poly/MOS capacitor in which the processing steps thereof can be integrated into various BiCMOS integration schemes.
In the field of semiconductor device manufacturing, CMOS (complementary metal oxide semiconductor) and BiCMOS (bipolar device and complementary metal oxide semiconductor) technologies have been widely used for integrating highly complex analog-digital subsystems onto a single chip. In such subsystems, high precision capacitors are typically required.
Several types of capacitors are available including Poly-Poly capacitors, MOS capacitors (also referred to in the art as diffusion-Poly capacitors), and metal-metal capacitors. In order to meet the demand for high precision capacitors in today""s generation of integrated devices, Poly-Poly capacitors have been increasingly used.
Despite its high precision, a Poly-Poly capacitor is a compromise between high cost and ideal capacitor characteristics since it is relatively easy to construct, and has electrical characteristics better than MOS capacitors, but inferior electrical characteristics to metal-metal capacitors. However, metal-metal capacitors are much more difficult to fabricate than are Poly-Poly capacitors.
Moreover, Poly-Poly capacitors are known to have a more linear V-C relationship than MOS capacitors. The dielectric for MOS capacitors results from an oxide that is thermally grown over a highly doped diffusion region. In contrast, the dielectric for a Poly-Poly capacitor is generally a deposited CVD oxide and reliability requirements cause the resulting oxide to be thicker than can be realized with a thermal oxide. Therefore, higher capacitance values generally result for MOS capacitors than Poly-Poly capacitors.
In view of the above remarks concerning Poly-Poly capacitors, it would be extremely beneficial if a Poly-Poly capacitor was developed that has improved capacitance per unit area. This goal is obtained in the present invention by stacking a Poly-Poly capacitor on top of a MOS capacitor. Such a capacitor is extremely useful in integrated and mixed signal applications.
One object of the present invention is to provide a BiCMOS device that includes at least a stacked Poly-Poly/MOS capacitor therein.
Another object of the present invention is to provide a stacked Poly-Poly/MOS capacitor that has a high capacitance associated therewith.
A further object of the present invention is to provide a stacked Poly-Poly/MOS capacitor that has a high voltage associated therewith.
A yet further object of the present invention is to provide a stacked Poly-Poly/MOS capacitor that can be fabricated utilizing process steps that can be easily integrated into existing BiCMOS processing schemes.
These and other objects and advantages are achieved in the present invention by forming a Poly-Poly capacitor on top of a MOS capacitor utilizing the top electrode of the MOS capacitor as the base electrode of the Poly-Poly capacitor.
In one aspect of the present invention, a stacked Poly-Poly/MOS capacitor having the above features is provided Specifically, the stacked Poly-Poly/MOS capacitor of the present invention comprises:
a semiconductor substrate having a region of a first conductivity-type formed in a surface thereof;
gate oxide formed on said semiconductor substrate overlaying said region of first conductivity-type;
a first polysilicon layer formed at least on said gate oxide layer, said first polysilicon layer being doped with an N or P-type dopant;
a dielectric layer formed on said first polysilicon layer; and
a second polysilicon layer formed on said dielectric layer, said second polysilicon layer being doped with the same or different dopant as the first polysilicon layer.
It is noted that the first layer of polysilicon serves as the top electrode of the MOS capacitor as well as the base plate, i.e., base electrode, of the Poly-Poly capacitor.
In one embodiment of the present invention, either the first layer of polysilicon or the second layer of polysilicon is comprised of SiGe.
In one highly preferred embodiment of the present invention, the second layer of polysilicon is comprised of SiGe.
In another embodiment of the present invention, the second layer of polysilicon and the region of first conductivity-type are coupled to a first electrical node and the first layer of polysilicon is coupled to a second electrical node. In this parallel wiring configuration, the stacked Poly-Poly/MOS capacitor of the present invention operates as a high capacitance capacitor since overall capacitance of the stacked capacitor equals the sum of the capacitance of the individual capacitors, i.e., the MOS capacitor and the Poly-Poly capacitor.
In still another embodiment of the present invention, either the first or second polysilicon layer of the capacitor is coupled to a first electrical node and the region of first conductivity-type is coupled to a second electrical node. In this series wiring configuration, the stacked Poly-Poly/MOS capacitor of the present invention operates as a high voltage capacitor since an inverse capacitance relationship between the two capacitors exists.
It is noted that the stacked Poly-Poly/MOS capacitor of the present invention is used as a component in a BiCMOS device. Thus, the stacked Poly-Poly/MOS capacitor of the present invention may be used in conjunction with conventional complementary metal oxide semiconductor (CMOS) devices, bipolar devices, capacitors or any other like devices that are typically present in a BICMOS device.
Another aspect of the present invention relates to a process of fabricating the above-defined stacked Poly-Poly/MOS capacitor. The process of the present invention can be easily implemented into existing BiCMOS processing schemes so as to provide a BiCMOS device that includes at least the stacked Poly-Poly/MOS capacitor of the present invention therein as one of the device components. Specifically, the method of the present invention comprises the steps of:
forming an oxide layer on a surface of a semiconductor substrate containing a region of first conductivity-type, said oxide layer overlaying said region of first conductivity-type;
(b) forming a first polysilicon layer on at least said oxide layer, said first polysilicon layer being doped with an N or P-type dopant;
(c) forming a dielectric layer on said first polysilicon layer; and
(d) forming a second polysilicon layer on said dielectric layer, said second polysilicon layer being doped with the same or different dopant as the first polysilicon layer.
The above method may include a wiring step and/or a passivation step which occur after step (d) above. The wiring step includes parallel wiring or series wiring. In parallel wiring, the top electrode, i.e., second polysilicon layer, of the Poly-Poly capacitor is coupled to the base plate, i.e., region of first conductivity-type, of the MOS capacitor through a first electrical node, and the first polysilicon layer is coupled to a second electrical node. In series wiring, the top electrode of the Poly-Poly capacitor or the base plate of the Poly-Poly capacitor is coupled to a first electrical node and the region-of first conductivity-type is coupled to a second electrical node.